Semiconductor package and method for making the same

ABSTRACT

A semiconductor package includes: a semiconductor substrate; an inner insulator layer formed on the substrate; at least one internal wiring extending from a front side of the substrate along one of lateral sides of the substrate to a rear side of the substrate; a first outer insulator layer disposed at the front side of the substrate, formed on the internal wiring, and formed with at least one wire-connecting hole; and a second outer insulator layer disposed at the rear side of the substrate, formed on the internal wiring, and formed with at least one wire-connecting hole which exposes a portion of the internal wiring.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority of Taiwanese application no. 097104403,filed on Feb. 1, 2008.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a semiconductor package and a method formaking the same, more particularly to a semiconductor package having awiring extending from a bonding pad along a front side and a lateralside of a semiconductor substrate to a rear side of the semiconductorsubstrate.

2. Description of the Related Art

Stacked-type semiconductor devices are devices that include stackedsemiconductor packages so as to achieve miniaturization purposes forelectronic appliances. Hence, there is a need to form a low profilesemiconductor package that is suitable for making a low profilestacked-type semiconductor device. In addition, the low profilesemiconductor package is required to maintain a high stability in theelectrical property thereof.

SUMMARY OF THE INVENTION

Therefore, an object of the present invention is to provide asemiconductor package that has a low profile and a high stability in theelectrical property thereof.

Another object of the present invention is to provide a method formaking the semiconductor package.

According to one aspect of this invention, a semiconductor packagecomprises: a semiconductor substrate having front and rear sides, twoopposite lateral sides transverse to the front and rear sides, apad-mounting face disposed at the front side, and at least one bondingpad formed on the pad-mounting face; an inner insulator layer formed onthe pad-mounting face and formed with at least one pad-aligned hole thatexposes the bonding pad; at least one internal wiring connected to thebonding pad, extending therefrom through the pad-aligned hole to thefront side of the semiconductor substrate, and further extending fromthe front side of the semiconductor substrate along one of the lateralsides of the semiconductor substrate to the rear side of thesemiconductor substrate, the internal wiring including a first segmentformed on the inner insulator layer, a second segment disposed at theone of the lateral sides of the semiconductor substrate, and a thirdsegment disposed at the rear side of the semiconductor substrate; afirst outer insulator layer disposed at the front side of thesemiconductor substrate and having a portion that is formed on the firstsegment of the internal wiring and that is formed with at least onefirst wire-connecting hole which exposes a portion of the first segmentof the internal wiring; and a second outer insulator layer disposed atthe rear side of the semiconductor substrate and having a portion thatis formed on the third segment of the internal wiring and that is formedwith at least one second wire-connecting hole which exposes a portion ofthe third segment of the internal wiring.

According to another aspect of this invention, a semiconductor packagecomprises: a semiconductor substrate having a pad-mounting face and atleast one bonding pad formed on the pad-mounting face; an innerinsulator layer formed on the pad-mounting face and formed with at leastone pad-aligned hole that exposes the bonding pad; a wire-defining layerformed on the inner insulator layer and formed with at least onewire-defining hole that exposes a portion of the inner insulator layerand that is in spatial communication with and that is transverse to thepad-aligned hole; at least one internal wiring connected to the bondingpad and extending therefrom through the pad-aligned hole and into thewire-defining hole; and an outer insulator layer formed on thewire-defining layer and the internal wiring and formed with at least onewire-connecting hole which exposes a portion of the internal wiring. Theinner insulator layer and the wire-defining layer cooperatively form astructure that has a trapezoidal cross-section.

According to yet another aspect of this invention, a method for makingsemiconductor packages comprises: forming a first inner insulator layeron a pad-mounting face of a semiconductor substrate; forming a pluralityof pad-aligned holes and a plurality of side holes in the first innerinsulator layer such that the pad-aligned holes expose bonding pads onthe pad-mounting face of the semiconductor substrate, respectively, andthat the side holes are disposed respectively at cutting lines of thesemiconductor substrate; forming a wire-defining layer on the firstinner insulator layer; forming a plurality of wire-defining holes in thewire-defining layer such that each of the wire-defining holes extendsbetween and communicates spatially with a respective one of thepad-aligned holes and a respective one of the side holes; forming aplurality of through-holes in the semiconductor substrate such that eachof the through-holes communicates spatially with a respective one of theside holes and extends through a rear face of the semiconductorsubstrate opposite to the pad-mounting face; forming a plurality offirst conductive traces such that each of the first conductive tracesfills a respective one of the pad-aligned holes to connect with arespective one of the bonding pads, and further fills a respective oneof the wire-defining holes, a respective one of the side holes, and arespective one of the through-holes; forming a second inner insulatorlayer on the rear face of the semiconductor substrate; forming aplurality of wire-extension holes in the second inner insulator layersuch that each of the wire-extension holes communicates spatially with arespective one of the through-holes; forming a plurality of secondconductive traces such that each of the second conductive traces fills arespective one of the wire-extension holes to connect with a respectiveone of the first conductive traces; forming a first outer insulatorlayer to cover the wire-defining layer and the first conductive traces;forming a plurality of wire-connecting holes in the first outerinsulator layer to expose portions of the first conductive traces,respectively; forming a second outer insulator layer to cover the secondinner insulator layer and the second conductive traces; forming aplurality of wire-connecting holes in the second outer insulator layerto expose portions of the second conductive traces, respectively;forming a plurality of conductive posts such that each of the conductiveposts fills a respective one of the wire-connecting holes in the firstouter insulator layer to connect with a respective one of the firstconductive traces and extends outwardly of the respective one of thewire-connecting holes in the first outer insulator layer; and cutting anassembly of the first and second inner insulator layers, the first andsecond outer insulator layers, the wire-defining layer, the first andsecond conductive traces, the conductive posts, and the semiconductorsubstrate along the cutting lines so as to form the semiconductorpackages.

According to a further aspect of this invention, a method for makingsemiconductor packages comprises: forming a plurality of upper recessesin a semiconductor substrate such that each of the upper recessesextends through a pad-mounting face of the semiconductor substrate andis disposed at a respective one of cutting lines of the semiconductorsubstrate; forming a first inner insulator layer on the pad-mountingface of the semiconductor substrate such that the first inner insulatorlayer fills the upper recesses; forming a plurality of pad-aligned holesin the first inner insulator layer such that the pad-aligned holesexpose bonding pads on the pad-mounting face of the semiconductorsubstrate, respectively, and a plurality of upper side holes in thefirst inner insulator layer such that the upper side holes are disposedrespectively at the cutting lines of the semiconductor substrate, eachof the upper side holes being defined by a hole-defining wall thatextends into a respective one of the upper recesses; forming a firstwire-defining layer on the first inner insulator layer; forming aplurality of first wire-defining holes in the first wire-de fining layersuch that each of the first wire-defining holes extends between andcommunicates spatially with a respective one of the pad-aligned holesand a respective one of the upper side holes; forming a plurality offirst conductive traces such that each of the first conductive tracesfills a respective one of the pad-aligned holes to connect with arespective one of the bonding pads, and further fills a respective oneof the first wire-defining holes and a respective one of the upper sideholes; forming a plurality of lower recesses in the semiconductorsubstrate such that each of the lower recesses extends through a rearface of the semiconductor substrate opposite to the pad-mounting faceand communicates spatially with a respective one of the upper recesses;forming a second inner insulator layer on the rear face of thesemiconductor substrate such that the second inner insulator layer fillsthe lower recesses; forming a plurality of lower side holes in thesecond inner insulator layer such that the lower side holes are disposedrespectively at the cutting lines of the semiconductor substrate, eachof the lower side holes communicating spatially with a respective one ofthe upper side holes and being defined by a hole-defining wall thatextends into a respective one of the lower recesses; forming a secondwire-defining layer on the second inner insulator layer; forming aplurality of second wire-defining holes in the second wire-defininglayer such that each of the second wire-defining holes communicatesspatially with and is transverse to a respective one of the lower sideholes; forming a plurality of second conductive traces such that each ofthe second conductive traces fills a respective one of the secondwire-defining holes and a respective one of the lower side holes toconnect with a respective one of the first conductive traces; forming afirst outer insulator layer to cover the first wire-defining layer andthe first conductive traces; forming a plurality of wire-connectingholes in the first outer insulator layer to expose portions of the firstconductive traces, respectively; forming a second outer insulator layerto cover the second wire-defining layer and the second conductivetraces; forming a plurality of wire-connecting holes in the second outerinsulator layer to expose portions of the second conductive traces,respectively; forming a plurality of conductive posts such that each ofthe conductive posts fills a respective one of the wire-connecting holesin the first outer insulator layer to connect with a respective one ofthe first conductive traces and extends outwardly of the respective oneof the wire-connecting holes in the first outer insulator layer; andcutting an assembly of the first and second inner insulator layers, thefirst and second outer insulator layers, the first and secondwire-defining layers, the first and second conductive traces, theconductive posts, and the semiconductor substrate along the cuttinglines so as to form the semiconductor packages.

According to still another aspect of this invention, a method for makingsemiconductor packages comprises: forming an inner insulator layer on apad-mounting face of a semiconductor substrate; forming a plurality ofpad-aligned holes in the inner insulator layer such that the pad-alignedholes expose bonding pads on the pad-mounting face of the semiconductorsubstrate, respectively, and a plurality of side holes in the innerinsulator layer such that the side holes are disposed respectively atcutting lines of the semiconductor substrate; forming a wire-defininglayer on the inner insulator layer; forming a plurality of wire-definingholes in the wire-defining layer such that each of the wire-definingholes extends between a respective one of the pad-aligned holes and arespective one of the side holes and communicates spatially with therespective one of the pad-aligned holes, and a plurality of sidethrough-holes in the wire-defining layer such that each of the sidethrough-holes is disposed at a respective one of the cutting lines andcommunicates spatially with a respective one of the side holes; forminga plurality of conductive traces such that each of the conductive tracesfills a respective one of the pad-aligned holes to connect with arespective one of the bonding pads, and further fills a respective oneof the wire-defining holes; forming an outer insulator layer to coverthe wire-defining layer and the conductive traces and to fill the sideholes and the side through-holes; forming a plurality of wire-connectingholes in the outer insulator layer to expose portions of the conductivetraces, respectively; forming a plurality of conductive posts such thateach of the conductive posts fills a respective one of thewire-connecting holes in the outer insulator layer to connect with arespective one of the conductive traces and extends outwardly of therespective one of the wire-connecting holes in the outer insulatorlayer; and cutting an assembly of the inner insulator layer, the outerinsulator layer, the wire-defining layer, the conductive traces, theconductive posts, and the semiconductor substrate along the cuttinglines so as to form the semiconductor packages. Each of the side holescooperates with the respective one of the side through-holes to form ahole shape that permits an assembly of the wire-forming layer and theinner insulator layer of each of the semiconductor packages to have atrapezoidal cross-section.

BRIEF DESCRIPTION OF THE DRAWINGS

Other features and advantages of the present invention will becomeapparent in the following detailed description of the preferredembodiments of the invention, with reference to the accompanyingdrawings, in which:

FIG. 1 is a partly sectional view of the first preferred embodiment of asemiconductor package according to this invention;

FIGS. 2 to 7 are fragmentary partly sectional views to illustrateconsecutive steps of a method for making the semiconductor package ofthe first preferred embodiment according to this invention;

FIG. 8 is a partly sectional view of a stacked-type semiconductor deviceformed by stacking two of the semiconductor packages of the firstpreferred embodiment;

FIG. 9 is a partly sectional view of the second preferred embodiment ofthe semiconductor package according to this invention;

FIGS. 10 to 14 are fragmentary partly sectional views to illustrateconsecutive steps of a method for making the semiconductor package ofthe second preferred embodiment according to this invention;

FIG. 15 is a partly sectional view of the third preferred embodiment ofthe semiconductor package according to this invention; and

FIGS. 16 to 18 are fragmentary partly sectional views to illustrateconsecutive steps of a method for making the semiconductor package ofthe third preferred embodiment according to this invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Before the present invention is described in greater detail withreference to the accompanying preferred embodiments, it should be notedherein that like elements are denoted by the same reference numeralsthroughout the disclosure.

FIG. 1 illustrates the first preferred embodiment of a semiconductorpackage according to the present invention. The semiconductor packageincludes: a semiconductor substrate 10 having front and rear sides 104,106, two opposite lateral sides transverse to the front and rear sides104, 106, a pad-mounting face 100 disposed at the front side 104, and atleast one bonding pad 102 formed on the pad-mounting face 100; a firstinner insulator layer 2 formed on the pad-mounting face 100 and formedwith at least one pad-aligned hole 20 that exposes the bonding pad 102;at least one internal wiring 9 connected to the bonding pad 102,extending therefrom through the pad-aligned hole 20 to the front side104 of the semiconductor substrate 10, and further extending from thefront side 104 of the semiconductor substrate 10 along one of thelateral sides of the semiconductor substrate 10 to the rear side 106 ofthe semiconductor substrate 10, the internal wiring 9 including a firstsegment 91 formed on the first inner insulator layer 2, a second segment92 disposed at the one of the lateral sides of the semiconductorsubstrate 10, and a third segment 93 disposed at the rear side 106 ofthe semiconductor substrate 10; a first outer insulator layer 80disposed at the front side 104 of the semiconductor substrate 10 andhaving a portion that is formed on the first segment 91 of the internalwiring 9 and that is formed with at least one first wire-connecting hole801 which exposes a portion of the first segment 91 of the internalwiring 9; and a second outer insulator layer 81 disposed at the rearside 106 of the semiconductor substrate 10 and having a portion that isformed on the third segment 93 of the internal wiring 9 and that isformed with at least one second wire-connecting hole 811 which exposes aportion of the third segment 93 of the internal wiring 9.

The semiconductor package further includes a wire-defining layer 4formed on the first inner insulator layer 2 and formed with at least onewire-defining hole 40 that exposes a portion of the first innerinsulator layer 2. The first segment 91 of the internal wiring 9 extendsinto and through the wire-defining hole 40, and is formed on the portionof the first inner insulator layer 2 exposed by the wire-defining hole40. The first outer insulator layer 80 further has another portion thatis formed on the wire-defining layer 4.

The semiconductor substrate 10 further has a rear face 101 disposed atthe rear side 106 of the semiconductor substrate 10, and two oppositeside faces 103 disposed at the lateral sides, respectively, andinterconnecting the pad-mounting face 100 and the rear face 101. In thisembodiment, the second segment 92 of the internal wiring 9 is formed onone of the side faces 103 that is disposed at said one of the lateralsides. The third segment 93 of the internal wiring 9 is formed on therear face 101 of the semiconductor substrate 10.

The semiconductor package further includes a second inner insulatorlayer 6 that is formed on the rear face 101 of the semiconductorsubstrate 10 and that is formed with at least one wire-extension hole 60which exposes a portion of the rear face 101 of the semiconductorsubstrate 10. The third segment 93 of the internal wiring 9 extends intothe wire-extension hole 60, and is formed on the portion of the rearface 101 of the semiconductor substrate 10 exposed by the wire-extensionhole 60. The second outer insulator layer 81 further has another portionthat is formed on the second inner insulator layer 6.

The semiconductor package further includes at least one conductive post820 extending outwardly from the first segment 91 of the internal wiring9 through the first wire-connecting hole 801 in the first outerinsulator layer 80.

The first segment 91 of the internal wiring 9 includes a layer of aconductive paste 5 and a layer of a metal 7. The second segment 92 ofthe internal wiring 91 includes a layer of the conductive paste 5. Thethird segment 93 of the internal wiring 9 includes a layer of theconductive paste 5 and a layer of the metal 7. The bonding pad 102 isprovided with a metal layer 3 thereon. The conductive paste 5 of thefirst segment 91 of the internal wiring 9 is connected to the metallayer 3. Each of the metal layer and the layer of the metal 7 ispreferably a bi-layer structure of Ni/Au.

FIGS. 2 to 7 illustrate consecutive steps of a method for making thesemiconductor package of the first preferred embodiment according tothis invention.

The method includes the steps of: preparing a wafer 1 that includes thesemiconductor substrate 10 having a plurality of cutting lines (CL);forming the first inner insulator layer 2 of an insulator material, suchas polyimide, on the pad-mounting face 100 of the semiconductorsubstrate 10 of the wafer 1 (see FIG. 2) using spinning coatingtechniques; forming a plurality of the pad-aligned holes 20 and aplurality of side holes 21 in the first inner insulator layer 2 usingphotolithographic techniques such that the pad-aligned holes 20 exposethe bonding pads 102, respectively, and that the side holes 21 aredisposed respectively at the cutting lines (CL) (see FIG. 2); formingthe wire-defining layer 4 on the first inner insulator layer 2 (see FIG.2); forming a plurality of the wire-defining holes 40 in thewire-defining layer 4 using photolithographic techniques such that eachof the wire-defining holes 40 extends between and communicates spatiallywith a respective one of the pad-aligned holes 20 and a respective oneof the side holes 21 (see FIG. 3); forming a plurality of through-holes11 in the semiconductor substrate 10 using techniques, such as laserdrilling, such that each of the through-holes 11 communicates spatiallywith a respective one of the side holes 21 and extends through a rearface 101 of the semiconductor substrate 10 opposite to the pad-mountingface 100 (see FIG. 3); forming a plurality of first conductive traces901 such that each of the first conductive traces 901 fills a respectiveone of the pad-aligned holes 20 to connect with a respective one of thebonding pads 102, and further fills a respective one of thewire-defining holes 40, a respective one of the side holes 21, and arespective one of the through-holes 11 (see FIGS. 4 to 6); polishing therear face 101 of the semiconductor substrate 10 and forming the secondinner insulator layer 6 on the rear face 101 of the semiconductorsubstrate 10 (see FIG. 6); forming a plurality of the wire-extensionholes 60 in the second inner insulator layer 6 using photolithographictechniques such that each of the wire-extension holes 60 communicatesspatially with a respective one of the through-holes 11 (see FIG. 6);forming a plurality of second conductive traces 902 such that each ofthe second conductive traces 902 fills a respective one of thewire-extension holes 60 to connect with a respective one of the firstconductive traces 901 so as to form the internal wiring 9 of eachsemiconductor package (see FIG. 6); forming the first outer insulatorlayer 80 to cover the wire-defining layer 4 and the first conductivetraces 901 (see FIG. 7); forming a plurality of the firstwire-connecting holes 801 in the first outer insulator layer 80 usingphotolithographic techniques to expose portions of the first conductivetraces 901, respectively (see FIG. 7); forming the second outerinsulator layer 81 to cover the second inner insulator layer 6 and thesecond conductive traces 902 (see FIG. 7); forming a plurality of thesecond wire-connecting holes 811 in the second outer insulator layer 81using photolithographic techniques to expose portions of the secondconductive traces 902, respectively (see FIG. 7); forming a plurality ofthe conductive posts 820 such that each of the conductive posts 820fills a respective one of the first wire-connecting holes 801 in thefirst outer insulator layer 80 to connect with a respective one of thefirst conductive traces 901 and extends outwardly of the respective oneof the first wire-connecting holes 801 in the first outer insulatorlayer 80 (see FIG. 7); and cutting an assembly of the first and secondinner insulator layers 2, 6, the first and second outer insulator layers80, 81, the wire-defining layer 4, the first and second conductivetraces 901, 902, the conductive posts 820, and the semiconductorsubstrate 10 along the cutting lines (CL) so as to form thesemiconductor packages.

Each of the first conductive traces 901 is formed by filling therespective one of the pad-aligned holes 20, the respective one of thewire-defining holes 40, the respective one of the side holes 21, and therespective one of the through-holes 11 (see FIGS. 4 to 6) with theconductive paste 5, followed by forming the layer of the metal 7 on aportion of the conductive paste 5 that fills the respective one of thepad-aligned holes 20 and the respective one of the wire-defining holes40. Each of the second conductive traces 902 is formed by filling therespective one of the wire-extension holes 60 with the conductive paste5, followed by forming the layer of the metal 7 on the conductive paste5. The metal layer 3 is formed on each of the bonding pads 102 prior toformation of the wire-defining layer 4.

FIG. 8 illustrates a configuration of a stacked-type semiconductordevice formed by stacking two of the semiconductor packages of the firstpreferred embodiment. The conductive post 820 of one of thesemiconductor packages extends into the second wire-connecting hole 811in the second outer insulator layer 81 of the other of the semiconductorpackages to connect with the internal wiring 9 of the other of thesemiconductor packages.

FIG. 9 illustrates the second preferred embodiment of the semiconductorpackage according to the present invention. The second preferredembodiment differs from the previous embodiment in that the pad-mountingface 100 and portions of the side faces 103 of the semiconductorsubstrate 10 are covered by the first inner insulator layer 2, and thatthe rear face 101 and the remainder of the side faces 103 of thesemiconductor substrate 10 are covered by the second inner insulatorlayer 6. The first and second inner insulator layers 2, 6 cooperativelydefine two opposite side insulator layers 26 formed on the side faces103 of the semiconductor substrate 10, respectively. As such, in thisembodiment, the second segment 92 of the internal wiring 9 is formed onone of the side insulator layers 26 that is disposed at said one of thelateral sides of the semiconductor substrate 10, and the third segment93 of the internal wiring 9 is formed on the second inner insulatorlayer 6.

In this embodiment, the semiconductor package further includes a secondwire-defining layer 45 formed on the second inner insulator layer 6 andformed with at least one second wire-defining hole 450 that exposes aportion of the second inner insulator layer 6. The third segment 93 ofthe internal wiring 9 extends into and through the second wire-defininghole 450 in the second wire-defining layer 45, and is formed on theportion of the second inner insulator layer 6 exposed by the secondwire-defining hole 450. The second outer insulator layer 81 further hasanother portion that is formed on the second wire-defining layer 45.

FIGS. 10 to 14 illustrate consecutive steps of a method for making thesemiconductor package of the second preferred embodiment according tothis invention.

The method includes the steps of: forming a plurality of upper recesses105 in the semiconductor substrate 10 of the wafer 1 such that each ofthe upper recesses 105 extends through the pad-mounting face 100 of thesemiconductor substrate 10 and is disposed at a respective one of thecutting lines (CL) of the semiconductor substrate 10 (see FIG. 10);forming the first inner insulator layer 2 on the pad-mounting face 100of the semiconductor substrate such that the first inner insulator layer2 fills the upper recesses 105 (see FIG. 11); forming a plurality of thepad-aligned holes 20 in the first inner insulator layer 2 such that thepad-aligned holes 20 expose the bonding pads 102, respectively, and aplurality of upper side holes 21′ in the first inner insulator layer 2such that the upper side holes 21′ are disposed respectively at thecutting lines (CL) of the semiconductor substrate 10, each of the upperside holes 21′ being defined by a hole-defining wall that extends into arespective one of the upper recesses 105 (see FIG. 11); forming thefirst wire-defining layer 4 on the first inner insulator layer 2 (seeFIG. 12); forming a plurality of the first wire-defining holes 40 in thefirst wire-defining layer 4 such that each of the first wire-definingholes 40 extends between and communicates spatially with a respectiveone of the pad-aligned holes 20 and a respective one of the upper sideholes 21′ (see FIG. 12); forming a plurality of first conductive traces901 such that each of the first conductive traces 901 fills a respectiveone of the pad-aligned holes 20 to connect with a respective one of thebonding pads 102, and further fills a respective one of the firstwire-defining holes 40 and a respective one of the upper side holes 21′(see FIGS. 13 and 14); forming a plurality of lower recesses 106 in thesemiconductor substrate 10 such that each of the lower recesses 106extends through the rear face 101 of the semiconductor substrate 10 andcommunicates spatially with a respective one of the upper recesses 105(see FIG. 13); forming the second inner insulator layer 6 on the rearface 101 of the semiconductor substrate 10 such that the second innerinsulator layer 6 fills the lower recesses 106 (see FIG. 13); forming aplurality of lower side holes 61′ in the second inner insulator layer 6such that the lower side holes 61′ are disposed respectively at thecutting lines (CL) of the semiconductor substrate 10, each of the lowerside holes 61′ communicating spatially with a respective one of theupper side holes 21′ and being defined by a hole-defining wall thatextends into a respective one of the lower recesses 106 (see FIG. 13);forming the second wire-defining layer 45 on the second inner insulatorlayer 6 (see FIG. 13); forming a plurality of the second wire-definingholes 450 in the second wire-defining layer 45 such that each of thesecond wire-defining holes 450 communicates spatially with and istransverse to a respective one of the lower side holes 61′ (see FIG.13); forming a plurality of second conductive traces 902 such that eachof the second conductive traces 902 fills a respective one of the secondwire-defining holes 450 and a respective one of the lower side holes 61′to connect with a respective one of the first conductive traces 901 (seeFIG. 14); forming the first outer insulator layer 80 to cover the firstwire-defining layer 4 and the first conductive traces 901 (see FIG. 14);forming a plurality of the first wire-connecting holes 801 in the firstouter insulator layer 80 to expose portions of the first conductivetraces 901, respectively (see FIG. 14); forming a second outer insulatorlayer 81 to cover the second wire-defining layer 45 and the secondconductive traces 902 (see FIG. 14); forming a plurality ofwire-connecting holes 811 in the second outer insulator layer 81 toexpose portions of the second conductive traces 902, respectively (seeFIG. 14); forming a plurality of conductive posts 820 such that each ofthe conductive posts 820 fills a respective one of the firstwire-connecting holes 801 in the first outer insulator layer 80 toconnect with a respective one of the first conductive traces 901 andextends outwardly of the respective one of the first wire-connectingholes 801 in the first outer insulator layer 80 (see FIG. 14); andcutting an assembly of the first and second inner insulator layers 2, 6,the first and second outer insulator layers 80, 81, the first and secondwire-defining layers 4, 45, the first and second conductive traces 901,902, the conductive posts 820, and the semiconductor substrate 10 alongthe cutting lines (CL) so as to form the semiconductor packages.

FIG. 15 illustrates the third preferred embodiment of the semiconductorpackage according to the present invention. The semiconductor package ofthe third preferred embodiment includes: a semiconductor substrate 10having a pad-mounting face 100 and at least one bonding pad 102 formedon the pad-mounting face 100; an inner insulator layer 2 formed on thepad-mounting face 100 and formed with at least one pad-aligned hole 20that exposes the bonding pad 102; a wire-defining layer 4 formed on theinner insulator layer 2 and formed with at least one wire-defining hole40 that exposes a portion of the inner insulator layer 2 and that is inspatial communication with and that is transverse to the pad-alignedhole 20; at least one internal wiring 9 connected to the bonding pad 102and extending therefrom through the pad-aligned hole 20 and into thewire-defining hole 40; and an outer insulator layer 80 formed on thewire-defining layer 4 and the internal wiring 9 and formed with at leastone wire-connecting hole 801 which exposes a portion of the internalwiring 9. The inner insulator layer 2 and the wire-defining layer 4cooperatively form a structure that has a trapezoidal cross-section.

The bonding pad 102 is provided with a metal layer 3 that is connectedto the internal wiring 9. The internal wiring 9 includes a layer of aconductive paste 5.

FIGS. 16 to 19 illustrate consecutive steps of a method for making thesemiconductor package of the third preferred embodiment according tothis invention.

The method includes the steps of: forming the inner insulator layer 2 onthe pad-mounting face 100 of the semiconductor substrate 10 of the wafer1 (see FIG. 16) using spinning coating techniques; forming a pluralityof the pad-aligned holes 20 in the inner insulator layer 2 such that thepad-aligned holes 20 expose bonding pads 102 on the pad-mounting face100 of the semiconductor substrate 10, respectively, and a plurality ofside holes 22 in the inner insulator layer 2 such that the side holes 22are disposed respectively at cutting lines (CL) of the semiconductorsubstrate 10 using photolithographic techniques (see FIG. 16); forming ametal layer 3 on each of the bonding pads 102 (see FIG. 16); forming thewire-defining layer 4 on the inner insulator layer 2 (see FIG. 17);forming a plurality of the wire-defining holes 40 in the wire-defininglayer 4 such that each of the wire-defining holes 40 extends between arespective one of the pad-aligned holes 20 and a respective one of theside holes 22 and communicates spatially with the respective one of thepad-aligned holes 20, and a plurality of side through-holes 41 in thewire-defining layer 4 such that each of the side through-holes 41 isdisposed at a respective one of the cutting lines (CL) and communicatesspatially with a respective one of the side holes 22 (see FIG. 17);forming a plurality of conductive traces 901 of the conductive paste 5such that each of the conductive traces 901 fills a respective one ofthe pad-aligned holes 20 to connect with a respective one of the bondingpads 102, and further fills a respective one of the wire-defining holes40 (see FIG. 18); forming an outer insulator layer 80 to cover thewire-defining layer 4 and the conductive traces 901 and to fill the sideholes 22 and the side through-holes 41; forming a plurality ofwire-connecting holes 801 in the outer insulator layer 80 to exposeportions of the conductive traces 901, respectively (see FIG. 18);forming a plurality of conductive posts 820 such that each of theconductive posts 820 fills a respective one of the wire-connecting holes801 in the outer insulator layer 80 to connect with a respective one ofthe conductive traces 901 and extends outwardly of the respective one ofthe wire-connecting holes 801 in the outer insulator layer 80 (see FIG.18); and cutting an assembly of the inner insulator layer 2, the outerinsulator layer 80, the wire-defining layer 4, the conductive traces901, the conductive posts 820, and the semiconductor substrate along thecutting lines (CL) so as to form the semiconductor packages. Each of theside holes 22 cooperates with the respective one of the sidethrough-holes 41 to form a hole shape that permits an assembly of thewire-forming layer 4 and the inner insulator layer 2 of each of thesemiconductor packages to have a trapezoidal cross-section.

By forming the internal wiring 9, which extends from the bonding pad 102along the front side and the lateral side of the semiconductor substrate10 to the rear side of the semiconductor substrate 10, the semiconductorpackage thus formed can achieve a relatively low profile configurationand a high stability in the electrical property thereof and thus achievethe miniaturization of the stacked-type semiconductor device.

While the present invention has been described in connection with whatare considered the most practical and preferred embodiments, it isunderstood that this invention is not limited to the disclosedembodiments but is intended to cover various arrangements includedwithin the spirit and scope of the broadest interpretations andequivalent arrangements.

What is claimed is:
 1. A semiconductor package comprising: asemiconductor substrate having a pad-mounting face and at least onebonding pad formed on said pad-mounting face; an inner insulator layerformed on said pad-mounting face and formed with at least onepad-aligned hole that exposes said bonding pad; a wire-defining layerformed on said inner insulator layer and formed with at least onewire-defining hole that exposes a portion of said inner insulator layerand that is in spatial communication with and that is transverse to saidpad-aligned hole; at least one internal wiring connected to said bondingpad and extending therefrom through said pad-aligned hole and into saidwire-defining hole; and an outer insulator layer formed on saidwire-defining layer and said internal wiring and formed with at leastone wire-connecting hole which exposes a portion of said internalwiring; wherein said inner insulator layer and said wire-defining layercooperatively form a structure that has a trapezoidal cross-section. 2.The semiconductor package of claim 1, further comprising at least oneconductive post extending outwardly from said internal wiring throughsaid wire-connecting hole.
 3. The semiconductor package of claim 1,wherein said internal wiring is made from a conductive paste.
 4. Thesemiconductor package of claim 1, wherein said bonding pad is providedwith a metal layer thereon, said internal wiring being connected to saidmetal layer.
 5. A method for making semiconductor packages, comprising:forming an inner insulator layer on a pad-mounting face of asemiconductor substrate; forming a plurality of pad-aligned holes in theinner insulator layer such that the pad-aligned holes expose bondingpads on the pad-mounting face of the semiconductor substrate,respectively, and a plurality of side holes in the inner insulator layersuch that the side holes are disposed respectively at cutting lines ofthe semiconductor substrate; forming a wire-defining layer on the innerinsulator layer; forming a plurality of wire-defining holes in thewire-defining layer such that each of the wire-defining holes extendsbetween a respective one of the pad-aligned holes and a respective oneof the side holes and communicates spatially with the respective one ofthe pad-aligned holes, and a plurality of side through-holes in thewire-defining layer such that each of the side through-holes is disposedat a respective one of the cutting lines and communicates spatially witha respective one of the side holes; forming a plurality of conductivetraces such that each of the conductive traces fills a respective one ofthe pad-aligned holes to connect with a respective one of the bondingpads, and further fills a respective one of the wire-defining holes;forming an outer insulator layer to cover the wire-defining layer andthe conductive traces and to fill the side holes and the sidethrough-holes; forming a plurality of wire-connecting holes in the outerinsulator layer to expose portions of the conductive traces,respectively; forming a plurality of conductive posts such that each ofthe conductive posts fills a respective one of the wire-connecting holesin the outer insulator layer to connect with a respective one of theconductive traces and extends outwardly of the respective one of thewire-connecting holes in the outer insulator layer; and cutting anassembly of the inner insulator layer, the outer insulator layer, thewire-defining layer, the conductive traces, the conductive posts, andthe semiconductor substrate along the cutting lines so as to form thesemiconductor packages; wherein each of the side holes cooperates withthe respective one of the side through-holes to form a hole shape thatpermits an assembly of the wire-forming layer and the inner insulatorlayer of each of the semiconductor packages to have a trapezoidalcross-section.
 6. The method of claim 5, further comprising forming ametal layer on each of the bonding pads prior to formation of thewire-defining layer.